1. Field of the Invention
This invention relates generally to the field of semiconductor microprocessors, and, more particularly, to the way that xe2x80x9cordinaryxe2x80x9d floating point data representations are distinguished from xe2x80x9cextraordinaryxe2x80x9d floating point data representations.
2. Description of the Related Art
Floating point data can typically have different representations. Commonly, a user conforming, for example, to the standard Institute of Electrical and Electronic Engineers (IEEE) formats will provide data to a microprocessor in single precision real, double precision real or extended precision real formats. Because of the difficulty in performing mixed format arithmetic operations (e.g., multiplication of a single precision real number by a double precision real number), many microprocessors convert floating point data to a predetermined standard format before beginning any operation. All the arithmetic operations are then performed, using the data converted to the predetermined standard format. After all arithmetic operations have been completed, the result is usually converted back to any desired user format.
A floating point number A includes a significand (or mantissa or fraction) Sa and an exponent Ea. The value of the floating point number A is given by the equation A=SarEa where r is the radix (or base) of the number system. The significand is usually normalized by requiring that the most significant digit (or the leftmost digit) be nonzero. Use of the binary radix (i.e., r=2) gives maximum accuracy, but may require more frequent normalization than use of higher radices.
Floating point numbers are capable of representing a wide range of values, from very large values to very small values, while maintaining the same precision throughout. Although a variety of data types are possible, floating point numbers usually assume one of the standard IEEE formats shown in FIG. 1. For example, FIG. 1 shows a 32-bit single precision real binary number, according to the IEEE 754 Standard (IEEE Standard for Floating-Point Arithmetic, IEEE Std 754-1985, reaffirmed 1990), having a sign S bit 10, a biased exponent E(8) portion 11, having 8 bits, and a significand F(23) (or mantissa or fraction) portion 12, having 23 bits. The normalized value of such a 32-bit single precision real binary number, according to the IEEE 754 Standard, is given by the equation A32sp=(xe2x88x921)S1.F(23)2E(8)xe2x88x92127 where the xe2x80x9cbinary pointxe2x80x9d (similar to the decimal point in base-10) is immediately to the right of the most significant bit. Similarly, FIG. 1 shows a 64-bit double precision real binary number, according to the IEEE 754 Standard, having a sign S bit 13, a biased exponent E(11) portion 14, having 11 bits, and a significand F(52) (or mantissa or fraction) portion 15, having 52 bits. The normalized value of such a 64-bit double precision real binary number, according to the IEEE 754 Standard, is given by the equation A64dp=(xe2x88x921)s1.F(52)2E(11)xe2x88x921023 where the binary point is again immediately to the right of the most significant bit.
FIG. 1 shows an 80-bit extended double precision real binary number, according to the IEEE 754 Standard, having a sign S bit 19, a biased exponent E(15) portion 17, having 15 bits, and a remaining portion, having 64 bits, including a significand F(63) (or mantissa or fraction) portion 18, having 63 bits and a single J-bit). The normalized value of such an 80-bit extended precision real binary number, according to the IEEE 754 Standard, is given by the equation A80ep=(xe2x88x921)S(i)J1.F(63)2E(15)xe2x88x9216383 where i is the square root of (xe2x88x921) and the binary point is still immediately to the right of the most significant bit.
FIG. 1 also shows an exemplary 86-bit internal binary representation useful in a microprocessor, having a sign S bit, a biased exponent E(17) portion 20, having 17 bits, and a remaining portion, having 68 bits, including a significand F(63) (or mantissa or fraction) portion 21, having 63 bits, a single I-bit, a single J-bit, a single Guard bit, a single Round bit and a single Sticky bit. By using such an internal representation that is larger than any of the IEEE Standard formats that a microprocessor can accommodate, overflow and rounding errors that normally occur during arithmetic operations may be virtually eliminated, for example.
The B-bit biased exponent Ebias(B) ranges from 0 to 2Bxe2x88x921 in the IEEE Standard format binary floating point representations because the relative sizes of the biased exponents Ebias(B) of different floating point numbers are then simpler to determine. The effective value of the exponent of the binary radix (r=2) is determined by subtracting a bias value 2(Bxe2x88x921)xe2x88x921 from the B-bit biased exponent value Ebias(B). The range of effective values of the exponent of the binary radix (r=2) is from xe2x88x92(2(Bxe2x88x921)xe2x88x921) to 2(Bxe2x88x921), corresponding to the B-bit biased exponent Ebias(B) range of from 0 to 2Bxe2x88x921, respectively.
The IEEE Standard format binary floating point representations having B-bit biased exponents Ebias(B) ranging from 1 to 2Bxe2x88x922 are xe2x80x9cordinaryxe2x80x9d or xe2x80x9cnonexceptionalxe2x80x9d binary floating point representations. The IEEE Standard format binary floating point representations having B-bit biased exponents Ebias(B) of 0 or 2Bxe2x88x921 are xe2x80x9cextraordinaryxe2x80x9d or xe2x80x9cexceptionalxe2x80x9d binary floating point representations. A B-bit biased exponent value Ebias(B)=0 in the IEEE Standard format binary floating point representations serves as a flag or token for the number 0 (if the significand value is also 0) and for denormalized or subnormalized numbers (if the significand value is not also 0). A B-bit biased exponent value Ebias(B)=2Bxe2x88x921 in the IEEE Standard format binary floating point representations serves as a flag or token for infinity (if the significand value is 0) and for xe2x80x9cNot a Numberxe2x80x9d (NaN) indicators (if the significand value is not 0).
The conversion between different floating point representation formats is a low-level, performance-critical operation. As such, the conversion between different floating point representation formats is typically performed by various floating point hardware circuits. In some cases, however, the floating point hardware circuits cannot perform the conversion between different floating point representation formats because of the coincidence of the conversion with other system events, such as a cache line split on a memory operand, for example. In these cases, a floating point software handler performs the conversion between different floating point representation formats. Doing this conversion involves two relatively independent operations: (1) rounding the significand, and (2) converting the exponent.
As described above, the exponent field is made up of B bits, giving 2B possible binary exponent representations that each belong to one of two classes of representations: xe2x80x9cordinaryxe2x80x9d binary floating point representations, corresponding to an actual exponent for a binary-encoded floating point number, and xe2x80x9cextraordinaryxe2x80x9d binary floating point representations, corresponding to entities such as zero, infinity and xe2x80x9cNot a Numberxe2x80x9d (NaN) that are not otherwise readily encoded by binary floating point representations. When converting a floating point quantity between two different representations, the function to be applied to the exponent field depends on the respective class of the binary floating point representation. It would be desirable to distinguish, and to make distinctions between, the two classes of binary floating point representations, to discriminate quickly and reliably between the xe2x80x9cordinaryxe2x80x9d and the xe2x80x9cextraordinaryxe2x80x9d binary floating point representations and to detect, and to filter out, the xe2x80x9cextraordinaryxe2x80x9d binary floating point representations, as needed.
The cases where the floating point hardware circuits cannot perform the conversion between different floating point representation formats are implementation-dependent and may not be self-evident. The cases where the floating point hardware circuits cannot perform the conversion between different floating point representation formats may also be frequent enough that having an inadequate floating point software assist can affect the over-all performance of the whole system.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method for distinguishing an ordinary binary floating point number from an extraordinary binary floating point number is provided, the method including adding 1 to a B-bit biased exponent of a binary floating point number to produce a (B+1)-bit augmented exponent and sign-extending the (B+1)-bit augmented exponent to produce a (B+n)-bit transformed exponent. The method also includes testing the (B+n)-bit transformed exponent to determine if the (B+n)-bit transformed exponent is less than 2.